Maximum likelihood detector and wireless signal receiver with maximum likelihood detection function

Abstract

The present invention discloses an ML (Maximum Likelihood) detector comprising: a search value selecting circuit selecting a first-layer search value; and an ML detecting circuit. The ML detecting circuit executes the following steps: selecting K first-layer candidate values according to the first-layer search value, one of a reception signal and a derivative thereof, and one of a channel estimation signal and a derivative thereof; calculating K second-layer candidate values according to the K first-layer candidate values; determining whether to add P second-layer supplemental candidate value(s) and generating a decision; when the decision is affirmative, adding the P second-layer supplemental candidate values, generating P first-layer supplemental candidate values according to the P second-layer supplemental candidate values, and calculating log likelihood ratios (LLRs) according to the (K+P) first-layer and (K+P) second-layer candidate values; and when the decision is negative, calculating LLRs according to the K first-layer and K second-layer candidate values.

Claims

What is claimed is: 1 . A maximum likelihood detector (ML detector) configured to execute maximum likelihood detection (ML detection) according to one of a reception signal and a derivative thereof and according to one of a channel estimation signal and a derivative thereof, the ML detector comprising: a search value selecting circuit configured to select a first-layer search value which is not less than a predetermined threshold; and a maximum likelihood detecting circuit (ML detecting circuit) configured to execute at least the following steps: selecting K first-layer candidate signal values according to the first-layer search value, one of the reception signal and the derivative thereof, and one of the channel estimation signal and the derivative thereof, in which the K is an integer greater than one; calculating K second-layer candidate signal values according to the K first-layer candidate signal values; determining whether to add P second-layer supplemental candidate signal value(s) according to the K second-layer candidate signal values and thereby generating a decision result, in which the P is a positive integer; when the decision result is affirmative, adding the P second-layer supplemental candidate signal value(s), selecting P first-layer supplemental candidate signal values according to the P second-layer supplemental candidate signal value(s), and calculating log likelihood ratios (LLRs) according to the K first-layer candidate signal values, the K second-layer candidate signal values, the P first-layer supplemental candidate signal value(s) and the P second-layer supplemental candidate signal value(s); and when the decision result is negative, calculating LLRs according to the K first-layer candidate signal values and the K second-layer candidate signal values. 2 . The ML detector of claim 1 , wherein the step of determining whether to add the P second-layer supplemental candidate signal value(s) includes: determining whether every n th bit value of each of the K second-layer candidate signal values is identical according to the K second-layer candidate signal values, in which the n is an integer between 0 and (m−1) and the m is a number of bit(s) of each of the K second-layer candidate signal values; and when determining every n th bit value of each of the K second-layer candidate signal values is identical, adding the P second-layer supplemental candidate signal value(s). 3 . The ML detector of claim 1 , wherein the step of adding the P second-layer supplemental candidate signal value(s) and the step of selecting the P first-layer supplemental candidate signal value(s) include: calculating K differences according to the K first-layer candidate signal values and the K second-layer candidate signal values; selecting a second-layer reference candidate signal value among the K second-layer candidate signal values according to the K differences, in which the second-layer reference candidate signal value is associated with a first-layer reference candidate signal value among the K first-layer candidate signal values; adding the P second-layer supplemental candidate signal value(s) according to the second-layer reference candidate signal value; and making each of the P first-layer supplemental candidate signal value(s) equal to the first-layer reference candidate signal value. 4 . The ML detector of claim 3 , wherein the P is not greater than a number of bit(s) of the second-layer reference candidate signal value. 5 . The ML detector of claim 3 , wherein the step of selecting the second-layer reference candidate signal value includes: selecting the second-layer reference candidate signal value among the K second-layer candidate signal values according to a minimum of the K differences. 6 . The ML detector of claim 3 , wherein the step of adding the P second-layer supplemental candidate signal value(s) includes: executing a look-up-table operation according to the second-layer reference candidate signal value for accessing pre-stored data, so as to add the P second-layer supplemental candidate signal value(s) according to the pre-stored data. 7 . The ML detector of claim 3 , wherein on a constellation diagram each of the P second-layer supplemental candidate signal value(s) is in a horizontal or vertical direction of the second-layer reference candidate signal value, in which the constellation diagram is associated with a modulation type of the reception signal. 8 . A maximum likelihood detector (ML detector) configured to execute maximum likelihood detection (ML detection) according to one of a reception signal and a derivative thereof and according to one of a channel estimation signal and a derivative thereof, the ML detector comprising: a search value selecting circuit configured to select a first search value and a second search value, each of which is not less than a predetermined threshold; and a maximum likelihood detecting circuit (ML detecting circuit) configured to execute at least the following steps: selecting K 1 first-layer bit-one candidate signal values according to the first search value, one of the reception signal and the derivative thereof, and one of the channel estimation signal and the derivative thereof, in which the K 1 is an integer greater than one; calculating K 1 second-layer bit-zero candidate signal values according to the K 1 first-layer bit-one candidate signal values; selecting K 2 first-layer bit-zero candidate signal values according to the second search value, one of the reception signal and the derivative thereof, and one of a swap signal of the channel estimation signal and a derivative of the swap signal, in which the K 2 is an integer greater than one; calculating K 2 second-layer bit-one candidate signal values according to the K 2 first-layer bit-zero candidate signal values; and calculating log likelihood ratios (LLRs) according to the K 1 first-layer bit-one candidate signal values, the K 1 second-layer bit-zero candidate signal values, the K 2 first-layer bit-zero candidate signal values and the K 2 second-layer bit-one candidate signal values. 9 . The ML detector of claim 8 , wherein a modulation type of the reception signal is quadrature amplitude modulation (QAM) with a signal set of size M, and the predetermined threshold is an integer greater than M/4. 10 . The ML detector of claim 8 , wherein all n th bit values of the K 1 first-layer bit-one candidate signal values include one and zero, all n th bit values of the K 2 first-layer bit-zero candidate signal values include one and zero, the n is an integer between 0 and (m−1), and m is a number of bit(s) of each of the K 1 second-layer bit-zero candidate signal values and the K 2 second-layer bit-one candidate signal values. 11 . A wireless signal receiver with a maximum likelihood detection function (ML detection function), comprising: a Discrete Fourier Transform (DFT) circuit configured to convert a time-domain signal into a frequency-domain signal; a reference signal extraction circuit configured to generate an extraction reference signal according to the frequency-domain signal; a channel estimation circuit configured to generate a channel estimation signal according to the extraction reference signal; a data signal extraction circuit configured to generate an extraction data signal according to the frequency-domain signal; a signal detecting circuit configured to generate a detection signal according to the channel estimation signal and the extraction data signal, the signal detecting circuit including a maximum likelihood detector (ML detector) configured to execute at least the following steps: determining a first-layer search value; and a maximum likelihood detection step including: selecting K first-layer candidate signal values according to the first-layer search value, one of the extraction data signal and a derivative thereof, and one of the channel estimation signal and a derivative thereof, in which the K is an integer greater than one; calculating K second-layer candidate signal values according to the K first-layer candidate signal values; determining whether to add P second-layer supplemental candidate signal value(s) according to the K second-layer candidate signal values and thereby generating a decision result, in which the P is a positive integer; when the decision result is affirmative, adding the P second-layer supplemental candidate signal value(s), selecting P first-layer supplemental candidate signal value(s) according to the P second-layer supplemental candidate signal value(s), and calculating log likelihood ratios (LLRs) as at least a part of the detection signal according to the K first-layer candidate signal values, the K second-layer candidate signal values, the P first-layer supplemental candidate signal value(s) and the P second-layer supplemental candidate signal value(s); and when the decision result is negative, calculating LLRs as at least a part of the detection signal according to the K first-layer candidate signal values and the K second-layer candidate signal values; and a decoding circuit configured to generate a decoded signal according to the detection signal. 12 . The wireless signal receiver of claim 11 , wherein the step of determining whether to add the P second-layer supplemental candidate signal value(s) includes: determining whether every n th bit value of each of the K second-layer candidate signal values is identical according to the K second-layer candidate signal values, in which the n is an integer between 0 and (m−1) and the m is a number of bit(s) of each of the K second-layer candidate signal values; and when determining every n th bit value of each of the K second-layer candidate signal values is identical, adding the P second-layer supplemental candidate signal value(s). 13 . The wireless signal receiver of claim 11 , wherein the step of adding the P second-layer supplemental candidate signal value(s) and the step of selecting the P first-layer supplemental candidate signal value(s) include: calculating K differences according to the K first-layer candidate signal values and the K second-layer candidate signal values; selecting a second-layer reference candidate signal value among the K second-layer candidate signal values according to the K differences, in which the second-layer reference candidate signal value is associated with a first-layer reference candidate signal value among the K first-layer candidate signal values; adding the P second-layer supplemental candidate signal value(s) according to the second-layer reference candidate signal value; and making each of the P first-layer supplemental candidate signal value(s) equal to the first-layer reference candidate signal value. 14 . The wireless signal receiver of claim 11 , wherein the signal detecting circuit further includes: a swap operation decision unit configured to determine whether to execute a swap operation according to the channel estimation signal, and configured to output the channel estimation signal when determining not to execute the swap operation, and further configured to perform the swap operation to the channel estimation signal for outputting a swap signal of the channel estimation signal when determining to execute the swap operation.
BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to wireless signal reception technique, especially to wireless signal reception technique using maximum likelihood detection. 2. Description of Related Art [0002] Nowadays wireless communication technique is widely spread and users have more and more demand for data throughput. Therefore, this industry field keeps studying how to increase bandwidth usage efficiency under limited system bandwidth and raise system throughput. A market trend is using a spatial multiplexing transmission manner of multiple-input multiple-output (MIMO) technique which can greatly raise system throughput without engaging more bandwidth. This transmission manner gets a lot of attention recently. [0003] The spatial multiplexing transmission manner uses a plurality of antennas of a transmitter to transmit signals independent of one another through the same frequency band at the same time, while a receiver uses a plurality of antennas to receive and detect these signals. In order to achieve better demodulation efficiency, the receiver may use a maximum likelihood algorithm (ML algorithm). The ML algorithm could be understood as an algorithm in search of an optimum solution. The ML algorithm makes use of an exhaustive search manner to estimate an optimum solution of transmission signals among all possible solutions according to reception signals. However, the exhaustive search manner is not an efficient manner because it computes all of the possible solutions and takes a long time to measure processing latency, complexity and computation power. [0004] People who are interested in the prior arts may refer to the following literatures: (1) China patent application of publication number CN101582748A; and (2) Massimiliano Siti, Michael P. Fitz, “ A Novel Soft - Output Layered Orthogonal Lattice Detector for Multiple Antenna Communications ”, IEEE International Conference on Communications (ICC), 2006. SUMMARY OF THE INVENTION [0007] In consideration of the problems of the prior arts, an object of the present invention is to provide a maximum likelihood detector and a wireless signal receiver with a maximum likelihood detection function for making improvements over the prior arts. [0008] The present invention discloses a maximum likelihood detector (ML detector) configured to execute maximum likelihood detection (ML detection) according to one of a reception signal and a derivative thereof and according to one of a channel estimation signal and a derivative thereof. An embodiment of the ML detector comprises a search value selecting circuit and a maximum likelihood detecting circuit (ML detecting circuit). The search value selecting circuit is configured to select a first-layer search value which is not less than a predetermined threshold. The ML detecting circuit is configured to execute at least the following steps: selecting K first-layer candidate signal values according to the first-layer search value, one of the reception signal and the derivative thereof, and one of the channel estimation signal and the derivative thereof, in which the K is an integer greater than one; calculating K second-layer candidate signal values according to the K first-layer candidate signal values; determining whether to add P second-layer supplemental candidate signal value(s) according to the K second-layer candidate signal values and thereby generating a decision result, in which the P is a positive integer; when the decision result is affirmative, adding the P second-layer supplemental candidate signal value(s), selecting P first-layer supplemental candidate signal value(s) according to the P second-layer supplemental candidate signal value(s), and calculating log likelihood ratios (LLRs) according to the K first-layer candidate signal values, the K second-layer candidate signal values, the P first-layer supplemental candidate signal value(s) and the P second-layer supplemental candidate signal value(s); and when the decision result is negative, calculating LLRs according to the K first-layer candidate signal values and the K second-layer candidate signal values. [0009] Another embodiment of the aforementioned ML detector comprises a search value selecting circuit and an ML detecting circuit. The search value selecting circuit is configured to select a first search value and a second search value, each of which is not less than a predetermined threshold. The ML detecting circuit is configured to execute at least the following steps: selecting K 1 first-layer bit-one candidate signal values according to the first search value, one of a reception signal and a derivative thereof, and one of a channel estimation signal and a derivative thereof, in which the K 1 is an integer greater than one; calculating K 1 second-layer bit-zero candidate signal values according to the K 1 first-layer bit-one candidate signal values; selecting K 2 first-layer bit-zero candidate signal values according to the second search value, one of the reception signal and the derivative thereof, and one of a swap signal of the channel estimation signal and a derivative of the swap signal, in which the K 2 is an integer greater than one; calculating K 2 second-layer bit-one candidate signal values according to the K 2 first-layer bit-zero candidate signal values; and calculating log likelihood ratios (LLRs) according to the K 1 first-layer bit-one candidate signal values, the K 1 second-layer bit-zero candidate signal values, the K 2 first-layer bit-zero candidate signal values and the K 2 second-layer bit-one candidate signal values. [0010] The present invention also discloses a wireless signal receiver with a maximum likelihood detection function (ML detection function). An embodiment of the wireless signal receiver comprises: a Discrete Fourier Transform (DFT) circuit configured to convert a time-domain signal into a frequency-domain signal; a reference signal extraction circuit configured to generate an extraction reference signal according to the frequency-domain signal; a channel estimation circuit configured to generate a channel estimation signal according to the extraction reference signal; a data signal extraction circuit configured to generate an extraction data signal according to the frequency-domain signal; a signal detecting circuit configured to generate a detection signal according to the channel estimation signal and the extraction data signal; and a decoding circuit configured to generate a decoded signal according to the detection signal. The signal detecting circuit includes a maximum likelihood detector (ML detector) configured to execute at least the following steps: determining a first-layer search value; and a maximum likelihood detection step. The maximum likelihood detection step includes: selecting K first-layer candidate signal values according to the first-layer search value, one of the extraction data signal and a derivative thereof, and one of the channel estimation signal and a derivative thereof, in which the K is an integer greater than one; calculating K second-layer candidate signal values according to the K first-layer candidate signal values; determining whether to add P second-layer supplemental candidate signal value(s) according to the K second-layer candidate signal values and thereby generating a decision result, in which the P is a positive integer; when the decision result is affirmative, adding the P second-layer supplemental candidate signal value(s), selecting P first-layer supplemental candidate signal value(s) according to the P second-layer supplemental candidate signal value(s), and calculating log likelihood ratios (LLRs) as at least a part of the detection signal according to the K first-layer candidate signal values, the K second-layer candidate signal values, the P first-layer supplemental candidate signal value(s) and the P second-layer supplemental candidate signal value(s); and when the decision result is negative, calculating LLRs as at least a part of the detection signal according to the K first-layer candidate signal values and the K second-layer candidate signal values. [0011] These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiments that are illustrated in the various figures and drawings. BRIEF DESCRIPTION OF THE DRAWINGS [0012] FIG. 1 illustrates an embodiment of the wireless signal receiver with a maximum likelihood detection function according to the present invention. [0013] FIG. 2 shows a tree diagram of exhaustive search. [0014] FIG. 3 shows a tree diagram under a configuration of a Layer Orthogonal Lattice Detector. [0015] FIG. 4 illustrates an embodiment of the maximum likelihood detector of the present invention. [0016] FIG. 5 illustrates an embodiment of the signal detecting circuit of FIG. 4 . [0017] FIG. 6 illustrates an exemplary operation, which is executed by the maximum likelihood detector of FIG. 4 , with a constellation diagram. [0018] FIG. 7 shows a tree diagram associated with FIG. 6 . [0019] FIG. 8 illustrates an embodiment of the signal detecting circuit of FIG. 4 . [0020] FIG. 9 illustrates shown an optimum path associated with the minimum difference calculated by the maximum likelihood detector of FIG. 4 . [0021] FIG. 10 illustrates an exemplary implementation concept of the candidate signal value adding unit of FIG. 8 . [0022] FIG. 11 illustrates an example of insufficient second-layer candidate signal values. [0023] FIG. 12 illustrates a supplemental path associated with the minimum difference calculated by the maximum likelihood detector of FIG. 4 . [0024] FIG. 13 illustrates an embodiment of the signal detecting circuit of FIG. 4 . [0025] FIG. 14 illustrates an embodiment of the signal detecting circuit of FIG. 4 . [0026] FIG. 15 illustrates an embodiment of the second detecting circuit of FIG. 14 . DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0027] The following description is written by referring to terms acknowledged in this industrial field. If any term is defined in this specification, such term should be explained accordingly. [0028] The present disclosure includes a maximum likelihood detector (ML detector), a maximum likelihood detecting method (ML detecting method) and a wireless signal receiver with a maximum likelihood detection function (ML detection function) configured to operate by bit in the manner of soft decision to output a log likelihood ratio (LLR) to a decoding circuit for error correction. On account of that some element of the ML detector and the wireless signal receiver of the present disclosure could be known, the detail of such element will be omitted, provided that this omission has little to do with the written description and enablement requirements. Besides, the method of the present disclosure can be in the form of firmware and/or software which could be carried out by the hardware of the present disclosure or the equivalent thereof. The present invention is applicable to multiple-dimension or multiple-layer signal reception such as signal reception of a multiple-input multiple output (MIMO) communication system. Communication technique using MIMO, for example, includes Long-Term Evolution (LTE) technique, Wireless Local-Area Network (WLAN) technique, Worldwide Interoperability for Microwave Access (WiMax) technique, etc. For the convenience of understanding, the embodiments in this specification are described in accordance with applications of LTE communication system; however, the present invention can be applied to other kinds of communication systems. [0029] Please refer to FIG. 1 . FIG. 1 illustrates an embodiment of the wireless signal receiver with the ML detection function according to the present invention. The wireless signal receiver 100 of FIG. 1 comprises: a Discrete Fourier Transform (DFT) circuit 110 configured to convert a time-domain signal into a frequency-domain signal; a reference signal (i.e., ref. signal in FIG. 1 ) extraction circuit 120 configured to generate an extraction reference signal according to the frequency-domain signal; a channel estimation circuit 130 configured to generate an estimation signal according to the extraction reference signal; a data signal extraction circuit 140 configured to generate an extraction data signal according to the frequency-domain signal; a signal detecting circuit 150 configured to generate a detection signal according to the channel estimation signal and the extraction data signal; and a decoding circuit 160 configured to generate a decoded signal according to the detection signal. The signal detecting circuit 150 includes a maximum likelihood detector (ML detector) 152 configured to execute at least the following steps: determining a first-layer search value; and a maximum likelihood detection step (ML detection step). The ML detection step includes: selecting K first-layer candidate signal values according to the first-layer search value, one of the extraction data signal and a derivative thereof, and one of the channel estimation signal and a derivative thereof, in which the K is an integer greater than one; calculating K second-layer candidate signal values according to the K first-layer candidate signal values; determining whether to add P second-layer supplemental candidate signal value(s) according to the K second-layer candidate signal values and thereby generating a decision result, in which the P is a positive integer; when the decision result is affirmative, adding the P second-layer supplemental candidate signal value(s), selecting P first-layer supplemental candidate signal value(s) according to the P second-layer supplemental candidate signal value(s), and calculating log likelihood ratios (LLRs) as at least a part of the detection signal according to the K first-layer candidate signal values, the K second-layer candidate signal values, the P first-layer supplemental candidate signal value(s) and the P second-layer supplemental candidate signal value(s); and when the decision result is negative, calculating LLRs as at least a part of the detection signal according to the K first-layer candidate signal values and the K second-layer candidate signal values. An embodiment of the decoding circuit 160 includes a descrambler and a turbo decoder, in which the descrambler is configured to generate a descrambled signal according to the detection signal and the turbo decoder is configured to generate the decoded signal according to the descrambled signal. Each of the DFT circuit 110 , the reference signal extraction circuit 120 , the channel estimation circuit 130 , the data signal extraction circuit 140 and the decoding circuit 160 itself is a known or self-developed circuit. [0030] On the basis of the above, the time-domain signal is converted into the frequency-domain signal through DFT, and the extraction data signal Y n of the n th sub-carrier in the frequency domain can be expressed by a N R ×1 vector as shown below: [0000] Y n =H n X n +W n   (Eq. 1) [0000] in which H n stands for a N R ×N T channel matrix from the n th sub-carrier's point of view, X n stands for the N T ×1 transmission signal of the n th sub-carrier, W n stands for the n th sub-carrier's noise, N R is the number of reception antenna(s), and N T is the number of transmission antenna(s). This embodiment takes the signal of a sub-carrier as a to-be-processed unit; for the convenience of expression, in the following description, the suffix n is omitted. In addition, this embodiment relates to an application of two-transmission two-reception spatial multiplexing transmission, that is to say both the number of independent spatial streams at a transmission end and the number of independent spatial streams at a reception end being two (and each of N R and N T being not less than two). Accordingly, Eq. 1 can be simplified as follows: [0000] Y=HX+W   (Eq. 2) [0031] In an LTE system, a reference signal (RS) and a data signal are carried by different sub-carriers, and thus the channel estimation circuit 130 derives a channel response matrix Ĥ of a target data signal based on channel estimation, which is estimated according to the reference signal, in the manner of interpolation or extrapolation; then the signal detecting circuit 150 performs QR decomposition or the equivalent thereof to the matrix Ĥ as shown below: [0000] Ĥ=QR   (Eq. 3) [0000] in which Q is a unitary matrix and R is an upper triangular matrix. After the QR decomposition or the equivalent thereof is done, the signal detecting circuit 150 multiplies the reception signal Y (i.e., the aforementioned extraction data signal) by Q H (i.e., Hermitian matrix of matrix Q) or executes an equivalent calculation to obtain a signal Z as follows: [0000] Z≡Q H Y=Q H ( HX+W )= Q H ( QRX+W )= RX+W′   (Eq. 4) [0000] in which W′≡Q H W. Afterward, the ML detector 152 calculates a log likelihood ratio (LLR) by bit according to the signal Z of Eq. 4. The calculation could be expressed as follows: [0000] L  ( b i | Y ) = min X ~ ∈ G  ( X b i = 1 )   Z - R  X ~  2 - min X ~ ∈ G  ( X b i = 0 )   Z - R  X ~  2 , ( Eq .  5 ) [0000] in which b i stands for i th bit, G(X b i =0 ) stands for a group of transmission signal(s) whose i th bit is/are 0, G(X b i =1 ) stands for a group of transmission signal(s) whose i th bit is/are 1, {tilde over (X)} stands for candidate signal value(s) of the calculation process, and the symbol “˜” is used to distinguish {tilde over (X)} from a real signal X. [0032] Eq. 5 can be regarded as an equation in search of an optimum solution, and the optimum solution can be found through exhaustive search as mentioned in the description of related art. If the modulation type of a transmission signal is M-QAM (i.e., quadrature amplitude modulation with a signal set of size M (which implies that the number of constellation points in a constellation diagram corresponding to such modulation type is M)), for two-layer independent data streams of two-transmission two-reception, the number of possible solutions of Eq. 5 (i.e., candidate signal value(s)) is M 2 which can be illustrated by a tree diagram as shown in FIG. 2 . [0033] In detail, since R is an upper triangular matrix, the operation in search of [0000] min X ~   Z - R  X ~  2 [0000] can be simplified. Firstly, [0000] min X ~   Z - R  X ~  2 [0000] can be decomposed as follows: [0000] min X ~   Z - R  X ~  2 = min X ~   [ Z 0 Z 1 ] - [ R 00 R 01 0 R 11 ] [ X ~ 0 X ~ 1 ]  2 = min X ~  [  Z 0 - R 00  X ~ 0 - R 01  X ~ 1  2 +  Z 1 - R 11  X ~ 1  2 ] ( Eq .  6 ) [0000] Since the square of an absolute value is not less than zero, ∥Z−R{tilde over (X)}∥ 2 will be the minimum with a selected {tilde over (X)} 1 when the following equation is true: [0000] X ~ 0 = Γ [ Z 0 - R 01  X ~ 1 R 00 ] ( Eq .  7 ) [0000] in which Γ[ ] stands for a quantizer. In other words, after {tilde over (X)} 1 is selected, the one and only solution derived from Eq. 7 is {tilde over (X)} 0 . The configuration associated with Eq. 6 and Eq. 7 is called a Layer Orthogonal lattice Detector (LOAD). Under such configuration, a tree diagram for search can be greatly simplified as shown in FIG. 3 . In a LOAD configuration corresponding to FIG. 3 , at the first layer are unfolded all possible solutions (M possible solutions) of {tilde over (X)} 1 , and at the second layer is derived {tilde over (X)} 0 according to Eq. 7 directly; accordingly, there is no need to unfold all possible solutions of {tilde over (X)} 0 in comparison with FIG. 2 . As a result, the whole computation complexity is up to the number of possible solutions of {tilde over (X)} 1 unfolded at the first layer. [0034] A log likelihood ratio (LLR) of every bit can be obtained through the calculation of Eq. 5 associated with the LOAD configuration corresponding to FIG. 3 , which implies that a number of the LLRs is equal to a number of the bits of the transmission signal; afterward these LLRs are inputted to a decoder for error correction so as to complete a reception process. However, take M-QAM; the number of possible solutions (i.e., the number of {tilde over (X)} 1 unfolded at the first layer in FIG. 3 ) is M, and some of the possible solutions therein is unlikely to be correct and better to be removed from consideration for simplifying calculation. Therefore, the ML detector 152 of FIG. 1 does not calculate LLRs of the M possible solutions, but selects/determines a search value first and then executes an ML calculation according to the search value and one of the frequency-domain signal and the derivative thereof (e.g., the aforementioned extraction data signal) to generate the detection signal including LLR(s) as described in the preceding paragraph, in which the search value is associated with a search range, and the number of candidate signal value(s) in the search range (that is to say the number of constellation points within the search range in a constellation diagram corresponding to the modulation type) is not greater than the number of all candidate signal values of the modulation type (that is to say the number of all constellation points in the constellation diagram corresponding to the modulation type). In other words, the ML detector 152 in FIG. 1 unfolds only K possible solution(s) (i.e., K candidate signal values) of {tilde over (X)} 1 (or {tilde over (X)} 0 ) at the first layer, and since K≦M, lower computation complexity and power consumption can be realized without substantially reducing performance. It should be noted that in a reversed operation, the ML detector 152 may unfold possible solutions of {tilde over (X)} 0 at the first layer with the aid of a swap operation decision unit (which will be explained in the following paragraphs) and then unfold possible solutions of {tilde over (X)} 1 at the second layer. For the ease of understanding, most of the embodiments in the following description adopt a straight operation which unfolds possible solutions of {tilde over (X)} 1 at the first layer and then unfolds possible solutions of {tilde over (X)} 0 at the second layer. However, the reversed operation may be adopted according to implementer's discretion, and can be easily derived from the disclosure of the straight operation in this specification. [0035] In detail, an embodiment of the ML detector 152 is shown in FIG. 4 , including a search value selecting circuit 410 and a maximum likelihood detecting circuit (ML detecting circuit) 420 . The search value selecting circuit 410 is configured to determine the aforementioned first-layer search value. An example of the first-layer search value is not less than a predetermined threshold. A number of the first-layer candidate signal value(s), associated with the predetermined threshold, is not greater than a number of all first-layer candidate signal values of the modulation type. For instance, when the modulation type is M-QAM, a non-restrictive example of the first-layer search value is an integer greater than M/4, and another non-restrictive example of the first-layer search value is an integer between 4 and (√{square root over (M)}−1) 2 . The ML detecting circuit 420 is configured to execute the calculation of Eq. 8 and a look-up-table operation, which are described in the following paragraphs, to obtain the first-layer candidate signal value(s), and configured to execute the calculation of the aforementioned Eq. 7 to obtain the second-layer candidate signal value(s), and further configured to execute the calculation of the aforementioned Eq. 5 to generate the LLRs. [0036] An exemplary implementation of the signal detecting circuit 150 of FIG. 4 is shown in FIG. 5 , including: a QR decomposition unit 530 configured to execute the calculation of Eq. 3 or the equivalent thereof according to the aforementioned estimation signal (associated with or equal to the channel response matrix Ĥ); a signal generating unit 540 configured to execute the calculation of Eq. 4 or the equivalent thereof according to the aforementioned extraction data signal (associated with or equal to the aforementioned signal Y); the search value selecting circuit 410 ; and the ML detecting circuit 420 . In FIG. 5 , the ML detecting circuit 420 includes: a first-layer candidate signal value decision unit 522 configured to execute the calculation of Eq. 8 or the equivalent thereof according to the extraction data signal so as to generate a computation result, and configured to execute the following look-up-table operation or the equivalent thereof according to the computation result and the first-layer search value so as to generate an operation result; and a second-layer candidate signal value decision unit 524 configured to execute the calculation of Eq. 7 or the equivalent thereof according to the operation result so as to generate a calculation result including the operation result; and an LLR calculation unit 526 configured to execute the calculation of Eq. 5 or the equivalent thereof according to the calculation result. Each of the said QR decomposition unit 530 and signal generating unit 540 itself is a known or self-developed unit. [0037] The ML detecting circuit 420 selects the first-layer search value, which is associated with the search range, according to the pinpoint of a reception signal mapped on a constellation diagram corresponding to the modulation type. Based on Eq. 6, an exemplary implementation of the ML detecting circuit 420 includes a zero-forcing (ZF) equalizer, which is included in the candidate signal value decision unit 422 , to execute a ZF calculation as shown below for determining the pinpoint {tilde over (X)} 1,eq of {tilde over (X)} 1 mapped on a constellation diagram: [0000] X ~ 1 , eq = Z 1 R 11 ( Eq .  8 ) [0000] In light of the feature of a constellation diagram, the distance (that is to say difference) between each constellation point of the constellation diagram and the pinpoint {tilde over (X)} 1,eq can be determined in advance. [0038] Take 64-QAM of LTE for example. Fourteen sections can be defined as shown in Table 1 below according to the relation between the locations of the pinpoint {tilde over (X)} 1,eq (i.e., a reference value associated with the pinpoint {tilde over (X)} 1,eq ) and the constellation points. In each section of Table 1, the left-to-right order indicates that the distance between a constellation point in the section and the pinpoint {tilde over (X)} 1,eq gets farther by the order. With the constellation diagram of FIG. 6 , the pinpoint {tilde over (X)} 1,eq of {tilde over (X)} 1 mapped on the constellation diagram is clearly shown, in which the symbol “x” of the digits “1x1x1x”, “x0x1x1”, etc. can be zero or one. In the example of FIG. 6 , the real-part of {tilde over (X)} 1,eq is located between the section 2≦S≦3, and the real-parts of the constellation points in the section by the close-to-far order (corresponding to the aforementioned left-to-right order) are 3, 1, 5, −1, 7, −3, −5 and −7 which amount to eight possible solutions. Similarly, the imaginary-part of {tilde over (X)} 1,eq is located between the section −3≦S≦−2, and the imaginary-parts of the constellation points in the section by the close-to-far order are −3, −1, −5, 1, −7, 3, 5 and 7 which amount to eight possible solutions. Assuming that the search value selected/determined by the search value selecting circuit 410 is twenty-five (which implies that only twenty-five possible solutions of {tilde over (X)} 1 (or {tilde over (X)} 0 ) are unfolded by the ML detecting circuit 420 at the first layer), the ML detecting circuit 420 will pick five real-parts closest to the pinpoint {tilde over (X)} 1,eq and five imaginary-parts closest to the pinpoint {tilde over (X)} 1,eq to obtain 5×5=25 possible solutions (i.e., 25 first-layer candidate signal values) which can be understood as a search range (e.g., a range in a shape of rectangle or another form) surrounding the pinpoint {tilde over (X)} 1,eq (i.e., the center) in FIG. 6 , and all constellation points within this search range are the constellation points (e.g., those closest to the pinpoint {tilde over (X)} 1,eq ) calculated by the ML detecting circuit 420 when unfolding {tilde over (X)} 1 at the first layer; meanwhile, the constellation points without the search range are removed from consideration. Accordingly, the present embodiment can lower computation complexity as shown in the tree diagram of FIG. 7 . It should be noted that the present embodiment may obtain the combination of the picked real-parts and imaginary-parts (i.e., the said possible solutions) through a look-up-table operation accessing pre-stored data (e.g., the data of Table 1), so as to make the ML detecting circuit 420 calculate LLR(s) according to Eq. 5 more efficiently. [0000] TABLE 1 S < −6 −1 −5 −3 −1 1 3 5 7 −6 ≦ S < −5 −5 −7 −3 −1 1 3 5 7 −5 ≦ S < −4 −5 −3 −7 −1 1 3 5 7 −4 ≦ S < −3 −3 −5 −1 −7 1 3 5 7 −3 ≦ S < −2 −3 −1 −5 1 −7 3 5 7 −2 ≦ S < −1 −1 −3 1 −5 3 −7 5 7 −1 ≦ S < 0  −1 1 −3 3 −5 5 −7 7 0 ≦ S < 1 1 −1 3 −3 5 −5 7 −7 1 ≦ S < 2 1 3 −1 5 −3 7 −5 −7 2 ≦ S < 3 3 1 5 −1 7 −3 −5 −7 3 ≦ S < 4 3 5 1 7 −1 −3 −5 −7 4 ≦ S < 5 5 3 7 1 −1 −3 −5 −7 5 ≦ S < 6 5 7 3 1 −1 −3 −5 −7 6 ≦ S 7 5 3 1 −1 −3 −5 −7 [0039] Referring to FIG. 6 , it is obvious that the scope of the search range has dominant influence on the computation complexity. When the search range includes all constellation points (i.e., sixty-four constellation points in FIG. 6 ), the computation complexity of the present embodiment is equivalent to the computation complexity of the aforementioned LORD configuration. In other words, the computation complexity of the present embodiment is equal to or less than the computation complexity of the LORD configuration. Of course the scope of the search range can be set in advance, and can be modified according to a communication status. When the scope of the search range is set in advance, the first-layer search value is determined by the search value selecting circuit 410 in accordance with the aforementioned predetermined value; for instance, the search value is equal to the predetermined value. When the scope of the search range is set according to the communication status, the index of the communication status (i.e., the aforementioned communication index) could be associated with at least one of a signal-to-noise ratio, sub-carrier reception signal energy strength, channel energy strength, channel correlation, channel estimation precision and interference energy strength, etc. When the modulation type is M-QAM, a non-restrictive example of the search value is an integer greater than M/4, and another non-restrictive example of the search value is an integer between 4 and (√{square root over (M)}−1) 2 (i.e., 4≦search value≦(√{square root over (M)}−1) 2 ). [0040] On the basis of the above, when the scope of the search range is determined according to the communication status, the scope of the search range, for example, could be determined according to the signal-to-noise ratio (SNR) during the ML detecting circuit 420 executing the ZF calculation for determining the pinpoint {tilde over (X)} 1,eq of {tilde over (X)} 1 on the constellation diagram. The said SNR can be represented by the symbol γ, and expressed as follows: [0000] γ =  R 11  2 σ W 2 , ( Eq .  9 ) [0000] in which σ W 2 stands for noise energy which can be measured in a conventional way known in this field, and R 11 is one of the elements of the aforementioned upper triangular matrix R. The greater the γ, the more reliable the ZF calculation result of the ML detecting circuit 420 ; in this case, the search value selecting circuit 410 may select a smaller search value (i.e., smaller search range). On the other hand, the smaller the γ, the greater the search value (i.e., the greater search range) that the search value selecting circuit 410 may choose. In light of the above, the present embodiment may define one or more threshold(s) T g (g=1, 2, . . . , G), in which T g <T g+1 . As shown in Table 2, when γ is greater than some threshold T g (e.g., T 1 ), the search value selecting circuit 410 will adopt a smaller search value (e.g., K 2 ), in which K G+1 <K G < . . . <K 2 <K 1 . [0000] TABLE 2 γ < T 1 K 1 T 1 ≦ γ < T 2 K 2 . . . . . . T g ≦ γ < T g+1 K g . . . . . . T G ≦ γ K G+1 [0041] In addition to the SNR (as shown in Eq. 9), the search value selecting circuit 410 is operable to select the search value (i.e., search range) according to other communication indexes. For instance, the search value selecting circuit 410 may select the search value according to channel correlation ρ which can be expressed as follows: [0000] ρ = h 1 H  h 2  h 1  2 2   h 2  2 2 ( eq .  10 ) [0042] In Eq. 10, h 1 stands for the first column of the channel response matrix Ĥ and h 2 stands for the second column of the matrix Ĥ. The greater the ρ (i.e., the smaller the 1/ρ), the more unreliable the ZF calculation result of {tilde over (X)} 1 calculated by the ML detecting circuit 420 ; in this case, the search value selecting circuit 410 may select a greater search value (i.e., greater search range). On the other hand, the smaller the ρ (i.e., the greater the 1/ρ), the smaller the search value (i.e., the smaller search range) that the search value selecting circuit 410 may choose. Therefore, when the communication index (e.g., γ, 1/ρ, etc.) is above a first threshold, the first-layer search value is a first value; when the communication index is below the first threshold, the first-layer search value is a second value. The first value is smaller than the second value, and the communication status represented by the communication index above the first threshold is better than the communication status represented by the communication index below the first threshold. [0043] On the basis of the above, when the first-layer search value is great enough, in the search range a set of n th bits of all first-layer candidate signal values will include a set of bit(s) being “1” and a set of bit(s) being “0”. Therefore, the ML detector 152 won't miss any first-layer candidate signal value that should be taken into consideration (as shown in FIG. 6 ). In other words, if the set of n th bits lacks the set of bit(s) being “0” or “1”, the ML detector 152 will find the set of bit(s) being “0” or “1” is null (i.e., an empty set) when calculating the LLRs, and this empty set will cause the ML detector 152 to fail to derive correction information when calculating the LLRs (because the concept of LLR calculation is to compare the probability of bit(s) being “1” with the probability of bit(s) being “0” for every bit set (i.e., every set of n th bits)), so that an extra computation process is necessary and performance loss is expected. However, even though none of the first-layer candidate signal values that should be taken into consideration is missing, since the second-layer candidate signal values are derived from the first-layer candidate signal values (as expressed by Eq. 7), some required second-layer candidate signal value(s) may be still missed, which means that an empty set will be found according to the currently-derived second-layer candidate signal values, due to a condition such as the irregular or concentrated distribution of the currently-derived second-layer candidate signal values. In consideration of the above, after the K first-layer and K second-layer candidate signal values are obtained, the ML detector 152 may further execute the aforementioned ML detection step. [0044] In the ML detection step, an example of the step of determining whether to add the P second-layer supplemental candidate signal value(s) includes: determining whether every n th bit value of each of the K second-layer candidate signal values is identical, in which the n is an integer between 0 and (m−1) and the m is a number of bit(s) of each of the K second-layer candidate signal values; and when determining every n th bit value of each of the K second-layer candidate signal values is identical, adding the P second-layer supplemental candidate signal value(s). For instance, as shown in FIG. 8 , the signal detecting circuit 150 further includes a candidate signal value adding unit 810 configured to determine whether to add supplemental candidate signal value(s). An embodiment of the candidate signal value adding unit 810 may generate a summation by summing the n th bit values of every candidate signal value up and then determine whether every n th bit value of every candidate signal value is identical according to the summation. More specifically, when the summation is zero, it is ascertained that every n th bit value of every candidate signal value is zero; when the summation is K, it is ascertained that every n th bit value of every candidate signal value is one. Another embodiment of the candidate signal value adding unit 810 may compare every n th bit value of every candidate signal value with a predetermined bit value, so as to determine whether every n th bit value of every candidate signal value is identical according to whether every comparison result is identical. These and other modifications can be implemented in the candidate signal value adding unit 810 . [0045] When the candidate signal value adding unit 810 decides to add supplemental candidate signal value(s), the adding unit 810 may add these supplemental candidate signal value(s) by executing the following steps: calculating K differences according to the K first-layer candidate signal values and the K second-layer candidate signal values (e.g., calculating K differences with Eq. 6 by introducing a first-layer candidate signal value and the corresponding second-layer candidate signal value thereof into Eq. 6 for K times); selecting a second-layer reference candidate signal value among the K second-layer candidate signal values according to the K differences, in which the second-layer reference candidate signal value is associated with a first-layer reference candidate signal value among the K first-layer candidate signal values; adding the P second-layer supplemental candidate signal value(s) according to the second-layer reference candidate signal value; and making each of the P first-layer supplemental candidate signal value(s) equal to the first-layer reference candidate signal value. For instance, the step of selecting the second-layer reference candidate signal value includes: calculating the K differences according to the K first-layer candidate signal values and the K second-layer candidate signal values; and treating a path between a first-layer and a second-layer candidate signal values, which achieve the minimum of the K differences, as an optimum path (as shown in FIG. 9 , in which u is one or zero, and ū is the reversed value of u); and treating the second-layer candidate signal value of the optimum path as the second-layer reference candidate signal value (e.g., “0100000” closest to the pinpoint {tilde over (X)} ū,eq in FIG. 10 and treating the first-layer candidate signal value of the optimum path as the first-layer reference signal candidate value. For another instance, the step of adding the P second-layer supplemental candidate signal value(s) according to the second-layer reference candidate signal value includes: executing a look-up-table operation, which accesses pre-stored data, according to the second-layer reference candidate signal value and thereby adding the P second-layer supplemental candidate signal value(s), in which on a constellation diagram each of the P second-layer supplemental candidate signal value(s) is in a horizontal or vertical direction of the second-layer reference candidate signal value (as shown in FIG. 10 ). The constellation diagram is associated with a modulation type of the reception signal, and the P is not greater than a number of bit(s) of the second-layer reference candidate signal value (e.g., the number of bits of the second-layer reference candidate signal value “010000” is six). [0046] The step of adding the P second-layer supplemental candidate signal value(s) is further explained below. Please refer to FIG. 9 and FIG. 10 . Take the i th bit of every {tilde over (X)} ū being j for example, in which each of ū and j could be “0” or “1”. According to the pinpoint {tilde over (X)} ū,Eq of {tilde over (X)} ū associated with the optimum path on a constellation diagram, each constellation point, whose i th bit is j , closest to {tilde over (X)} ū,Eq is treated as the second-layer supplemental candidate value. The process in search of supplemental candidate value(s) is dependent on the design of the constellation diagram. Take FIG. 10 (i.e., a constellation diagram of 64-QAM) for example. When the real-part of {tilde over (X)} ū,Eq is located within the section 2<Re[{tilde over (X)} ū,Eq ]≦3 and the imaginary-part of {tilde over (X)} ū,Eq is located within the section −3<Im[{tilde over (X)} ū,Eq ]≦−2 (and in this case, the bit value of the constellation point closest to {tilde over (X)} ū,Eq is “010000” (i.e., the second-layer reference candidate signal value) by an order from the most significant bit to the least significant bit), the constellation point being closest to {tilde over (X)} ū,Eq and having the reversed value of the most significant bit of “ 0 10000” is labeled as b 0 , the constellation point being closest to {tilde over (X)} ū,Eq and having the reversed value of the second significant bit of “0 1 0000” is labeled as b 1 , . . . , the constellation point being closest to {tilde over (X)} ū,Eq and having the reversed value of the least significant bit of “01000 0 ” is labeled as b 5 , and these constellation points b 0 , b 1 , b 2 , b 3 , b 4 and b 5 having the reversed values are eligible for supplemental candidate values. Such constellation points are located in a cross where the constellation point (i.e., “010000”) closest to {tilde over (X)} ū,Eq is centered. The relation between the said constellation points and {tilde over (X)} ū,Eq is listed in Tables 3˜5, in which ū, for example, is “1” in Tables 3˜5. Accordingly, through a look-up-table operation or an equivalent thereof, the candidate signal value adding unit 810 is capable of finding the constellation points, whose i th bit is j , closet to the pinpoint {tilde over (X)} ū,Eq . [0000] TABLE 3 nearest constellation point having the reversed value of the most significant bit Re[{tilde over (X)} 1, Eq ] ≦ 0 (1, Im[{tilde over (X)} 1 ]) 0 < Re[{tilde over (X)} 1, Eq ] (−1, Im[{tilde over (X)} 1 ]) Im[{tilde over (X)} 1, Eq ] ≦ 0 (Re[{tilde over (X)} 1 ], 1) 0 < Im[{tilde over (X)} 1, Eq ] (Re[{tilde over (X)} 1 ], −1) [0000] TABLE 4 nearest constellation point having the reversed value of the third significant bit Re[{tilde over (X)} 1, Eq ] ≦ −4 (−3, Im[{tilde over (X)} 1 ]) −4 < Re[{tilde over (X)} 1, Eq ] ≦ 0 (−5, Im[{tilde over (X)} 1 ]) 0 < Re[{tilde over (X)} 1, Eq ] ≦ 4 (5, Im[{tilde over (X)} 1 ] 0 < Re[{tilde over (X)} 1, Eq ] (3, Im[{tilde over (X)} 1 ]) Im[{tilde over (X)} 1, Eq ] ≦ 0 (Re[{tilde over (X)} 1 ], −3) −4 < Im[{tilde over (X)} 1, Eq ] ≦ 0 (Re[{tilde over (X)} 1 ], −5) 0 < Im[{tilde over (X)} 1, Eq ] ≦ 4 (Re[{tilde over (X)} 1 ], 5) 0 < Im[{tilde over (X)} 1, Eq ] (Re[{tilde over (X)} 1 ], 3) [0000] TABLE 5 nearest constellation point having the reversed value of the fifth significant bit Re[{tilde over (X)} 1, Eq ] ≦ −6 (−5, Im[{tilde over (X)} 1 ]) −6 < Re[{tilde over (X)} 1, Eq ] ≦ −4 (−7, Im[{tilde over (X)} 1 ] −4 < Re[{tilde over (X)} 1, Eq ] ≦ −2 (−1, Im[{tilde over (X)} 1 ]) −2 < Re[{tilde over (X)} 1, Eq ] ≦ 0 (−3, Im[{tilde over (X)} 1 ]) 0 < Re[{tilde over (X)} 1, Eq ] ≦ 2 (3, Im[{tilde over (X)} 1 ]) 2 < Re[{tilde over (X)} 1, Eq ] ≦ 4 (1, Im[{tilde over (X)} 1 ]) 4 < Re[{tilde over (X)} 1, Eq ] ≦ 6 (7, Im[{tilde over (X)} 1 ]) 6 < Re[{tilde over (X)} 1, Eq ] (5, Im[{tilde over (X)} 1 ]) Im[{tilde over (X)} 1, Eq ] ≦ −6 (Re[{tilde over (X)} 1 ], −5) −6 < Im[{tilde over (X)} 1, Eq ] ≦ −4 (Re[{tilde over (X)} 1 ], −7) −4 < Im[{tilde over (X)} 1, Eq ] ≦ −2 (Re[{tilde over (X)} 1 ], −1) −2 < Im[{tilde over (X)} 1, Eq ] ≦ 0 (Re[{tilde over (X)} 1 ], −3) 0 < Im[{tilde over (X)} 1, Eq ] ≦ 2 (Re[{tilde over (X)} 1 ], 3) 2 < Im[{tilde over (X)} 1, Eq ] ≦ 4 (Re[{tilde over (X)} 1 ], 1) 4 < Im[{tilde over (X)} 1, Eq ] ≦ 6 (Re[{tilde over (X)} 1 ], 7) 6 < Im[{tilde over (X)} 1, Eq ] (Re[{tilde over (X)} 1 ], 5) [0047] On the basis of the above, for instance, as shown in FIG. 11 , assuming that there are nine possible second-layer candidate signal values {tilde over (X)} ū , the real-part of the pinpoint {tilde over (X)} ū,eq is within the section 2<Re[{tilde over (X)} ū,eq ]≦3, the imaginary-part of {tilde over (X)} ū,eq is within the section −3<Im[{tilde over (X)} ū,eq ]≦−2, and the most and the second significant bits of every constellation point (i.e., candidate signal value) within the search range based on {tilde over (X)} ū,eq are 0 and 1 respectively, by looking data up in Table 3, the constellation point (i.e., b 0 “110010” in FIG. 10 ) being closest to the pinpoint {tilde over (X)} ū,eq and having the most significant bit “1” and the constellation point (i.e., b 1 “000001” in FIG. 10 ) being closest to the pinpoint {tilde over (X)} ū,eq and having the second significant bit “0” can be found as shown in FIG. 10 . After finding these two constellation points (i.e., second-layer supplemental candidate signal values), two supplemental paths can be added to the tree diagram of FIG. 9 as shown in FIG. 12 , so that the lack of possible solutions due to all most significant bits being short of bit “1” and all second significant bits being short of bit “0” is compensated. It should be noted that the distribution of the second-layer candidate signal value(s) of {tilde over (X)} ū may not be as regular as FIG. 11 . [0048] Please refer to FIG. 13 . The ML detector 152 is operable to execute the reversed operation (which unfolds possible solutions of {tilde over (X)} 0 at the first layer and then unfolds possible solutions of {tilde over (X)} 1 at the second layer) with the aid of a swap operation decision unit 1310 . The swap operation decision unit 1310 is operable to determine whether to execute a swap operation according to the channel estimation signal, operable to output the channel estimation signal to the QR decomposition unit 530 when determining not to execute the swap operation, and operable to perform the swap operation to the channel estimation signal when determining to execute the swap operation so as to output a swap signal of the channel estimation signal to the QR decomposition unit 530 . More specifically, an embodiment of the swap operation decision unit 1310 determines a priority order of signal detection according to the channel response matrix Ĥ of the channel estimation signal; for instance, the swap operation decision unit 1310 determines the priority order according to the energy of the matrix Ĥ. In an exemplary implementation, provided that the firstly unfolded signal is {tilde over (X)} u ({tilde over (X)} 1 or {tilde over (X)} 0 ) and the secondly unfolded signal is {tilde over (X)} ū ({tilde over (X)} 0 or {tilde over (X)} 1 ), when the square of the absolute value(s) of the first column in the matrix Ĥ is less than the square of the absolute value(s) of the second column in the matrix Ĥ, the swap operation decision unit 1310 will exchange the first column of Ĥ with the second column of Ĥ so as to output the swap signal of the channel estimation signal and thereby make the firstly unfolded signal be {tilde over (X)} 0 . When the square of the absolute value(s) of the first column in the matrix Ĥ is greater than the square of the absolute value(s) of the second column in the matrix Ĥ, the swap operation decision unit 1310 will output the matrix Ĥ (i.e., the channel estimation signal) and thereby make the firstly unfolded signal be {tilde over (X)} 1 . In brief, the swap operation decision unit 1310 is operable to make the signal of lower energy be detected first, so as to make the aforementioned first-layer search value be greater and thus decrease the probability of missing necessary candidate signal value(s). However, if the signal detecting circuit 150 always detects {tilde over (X)} 1 firstly or an equivalent of the signal detecting circuit 150 always detects {tilde over (X)} 0 firstly, the swap operation decision unit 1310 could be omitted. [0049] Please refer to FIG. 14 . FIG. 14 illustrates another embodiment of the signal detecting circuit 150 . In this embodiment, the signal detecting circuit executes the aforementioned straight operation with the first detecting circuit 1410 and executes the reversed operation with the second detecting circuit 1420 , in which an embodiment of the first detecting circuit 1410 is the ML detector 152 of FIG. 5 and an embodiment of the second detecting circuit 1420 is shown in FIG. 15 . In FIG. 15 , the swap unit 1510 will exchange the first column of the channel response matrix Ĥ with the second column of the matrix Ĥ so as to output the swap signal of the channel estimation signal. It should be noted that the first-layer search value generated by the first detecting circuit 1410 may be equal to or different from the first-layer search value generated by the second detecting circuit 1420 . For instance, both the first-layer search values generated by the first and second detecting circuits 1410 , 1420 respectively are K that is equal to or greater than the aforementioned predetermined threshold; or the two first-layer search values are K 1 , K 2 respectively, in which each of K 1 , K 2 is generated according to a communication index and not less than the predetermined threshold. Since K, K 1 , K 2 in the above instances are not less than the predetermined threshold, no supplemental candidate signal value has to be added. Of course the above-mentioned instances are not limits to the scope of the present invention. [0050] In the embodiment of FIG. 14 , LLRs are calculated according to (K+K) or (K1+K2) possible solutions; however, in the embodiment of FIG. 8 , LLRs are calculated according to only (K+P) possible solutions. Generally speaking, (K+P) is less than any of (K+K) and (K1+K2), and thus the embodiment of FIG. 8 is superior in low computation complexity and small circuit size. [0051] Since those of ordinary skill in the art can appreciate the detail and modification of the embodiments of FIG. 14 and FIG. 15 by referring to the explanation of the embodiments in the preceding paragraphs, repeated and redundant description is omitted without failing the written description and enablement requirements. It should be noted that there is no specific order for executing a plurality of steps in each embodiment of the present disclosure as long as such execution of the steps is practicable; in addition, one step could be composed of multiple sub-steps; these and other features can be found in or derived from the disclosure by those of ordinary skill in the art. [0052] In summary, the present invention is not complicated, and can achieve low latency, low computation complexity, low computation power consumption, small circuit size and no performance loss in comparison with the prior arts. [0053] The aforementioned descriptions represent merely the preferred embodiments of the present invention, without any intention to limit the scope of the present invention thereto. Various equivalent changes, alterations, or modifications based on the claims of present invention are all consequently viewed as being embraced by the scope of the present invention.

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